Phase-locked loops in which a clock signal is generated with a frequency which depends on a frequency of a reference signal and in particular may be a multiple of this are frequently used for generating clock signals of this kind. The reference signal can here be generated with great accuracy with a quartz oscillator, for example.
In FIG. 7 a conventional phase-locked loop of this kind is shown. A reference clock signal Fin, which is generated, for example, by a quartz oscillator, and a feedback signal Ffb are fed to a phase frequency detector 57. This activates a charge pump 58 depending on a phase and frequency difference between the reference clock signal Fin and the feedback signal Ffb. The output signal of the charge pump 58 is filtered by a loop filter 59, for example a low-pass filter, and the signal accordingly filtered is used to activate a voltage-controlled oscillator 60, which generates a clock signal Fout as a function of the filtered signal. The clock signal Fout is output and additionally fed to a frequency divider 50, in order to generate the feedback signal Ffb. The frequency divider 50 divides the frequency of the clock signal Fout by a specific factor. In this way it is achieved that the frequency of the clock signal Fout is greater than the frequency of the reference clock signal Fin by this specific factor.
As already initially described, the clock signals generated by phase-locked loops are used to control electronic circuits, for example in communications technology. As the circuits used there are for the most part highly integrated digital circuits, it is desirable as far as possible to dispense with analog components like the phase-locked loop illustrated in FIG. 7, in order as far as possible to be able to integrate all the parts of the circuit—for example in CMOS technology.
A partially digital solution for a phase-locked loop is illustrated in FIG. 8.
In this the reference clock signal Fin and the feedback signal Ffb, which in this case can be digital signals in each case, are fed to a digital frequency detector 56 and a digital phase detector 51. A digital or binary phase difference signal X, which is generated by the digital phase detector 51 and characterises a phase difference between the reference clock signal Fin and the feedback signal Ffb, is fed to a serial-parallel converter or decimator 52, in order to generate a decimated phase difference signal Z. The decimated phase difference signal Z is fed together with a frequency difference signal Y, generated by the frequency detector 56 as a function of a frequency difference between the reference clock signal Fin and the feedback signal Ffb, to a digital loop filter 53, which generates a digital corrective signal U. A digital-to-analog converter 54 generates from the digital corrective signal U an analog corrective signal with which a voltage- or current-controlled oscillator 55 is activated to generate the clock signal Fout. The clock signal Fout is again fed to a frequency divider 50, which in the present case may additionally comprise an analog-to-digital converter to convert the analog clock signal Fout into the digital feedback signal Ffb. A phase-locked loop of this kind can be integrated at least in its digital part. However, the digital-to-analog converter 54 provided in the phase-locked loop causes enlargement of the latency within the phase-locked loop, causing an increase in the noise of the phase-locked loop or the clock signal Fout generated by the phase-locked loop.